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? semiconductor components industries, llc, 2002 february, 2002 rev. 4 1 publication order number: ntd12n10/d ntd12n10 preferred device advance information power mosfet 12 amps, 100 volts nchannel enhancementmode dpak features ? sourcetodrain diode recovery time comparable to a discrete fast recovery diode ? avalanche energy specified ? i dss and r ds(on) specified at elevated temperature ? mounting information provided for the dpak package typical applications ? pwm motor controls ? power supplies ? converters maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit draintosource voltage v dss 100 vdc draintosource voltage (r gs = 1.0 m w ) v dgr 100 vdc gatetosource voltage continuous nonrepetitive (t p 10 ms) v gs v gsm 20 30 vdc vpk drain current continuous @ t a = 25 c drain current continuous @ t a =100 c drain current pulsed (note 3) i d i d i dm 12 7.0 36 adc apk total power dissipation derate above 25 c total power dissipation @ t a = 25 c (note 1) total power dissipation @ t a = 25 c (note 2) p d 56.6 0.38 1.47 1.07 watts w/ c watts watts operating and storage temperature range t j , t stg 55 to +175 c single pulse draintosource avalanche energy starting t j = 25 c (v dd = 50 vdc, v gs = 10 vdc, i l = 12 apk, l = 1.0 mh, r g = 25 w ) e as 75 mj thermal resistance junction to case junction to ambient (note 1) junction to ambient (note 2) r q jc r q ja r q ja 2.65 85 117 c/w maximum temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 1. when surface mounted to an fr4 board using 1 pad size, (cu area 1.127 in 2 ). 2. when surface mounted to an fr4 board using the minimum recommended pad size, (cu area 0.412 in 2 ). 3. pulse test: pulse width = 10 m s, duty cycle = 2%. this document contains information on a new product. specifications and information herein are subject to change without notice. 12 amperes 100 volts 165 m w @ v gs = 10 v device package shipping ordering information ntd12n10 dpak 75 units/rail case 369a dpak (bent lead) style 2 marking diagrams & pin assignments http://onsemi.com nchannel d s g 12n10 = device code y = year ww = work week t = mosfet 1 2 3 4 ntd12n101 dpak straight lead 75 units/rail ntd12n10t4 dpak 2500 tape & reel case 369 dpak (straight lead) style 2 yww t12n10 1 gate 3 source 2 drain 4 drain 1 2 3 4 1 gate 3 source 2 drain 4 drain yww t12n10 preferred devices are recommended choices for future use and best overall value.
ntd12n10 http://onsemi.com 2 electrical characteristics (t c = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics draintosource breakdown voltage (v gs = 0 vdc, i d = 250 m adc) temperature coefficient (positive) v (br)dss 100 135 vdc mv/ c zero gate voltage drain current (v gs = 0 vdc, v ds = 100 vdc, t j = 25 c) (v gs = 0 vdc, v ds = 100 vdc, t j = 125 c) i dss 5.0 50 m adc gatebody leakage current (v gs = 20 vdc, v ds = 0) i gss 100 nadc on characteristics gate threshold voltage v ds = v gs, i d = 250 m adc) temperature coefficient (negative) v gs(th) 2.0 3.1 7.5 4.0 vdc mv/ c static draintosource onstate resistance (v gs = 10 vdc, i d = 6.0 adc) (v gs = 10 vdc, i d = 6.0 adc, t j = 125 c) r ds(on) 0.130 0.250 0.165 0.400 w draintosource onvoltage (v gs = 10 vdc, i d = 12 adc) v ds(on) 1.62 2.16 vdc forward transconductance (v ds = 10 vdc, i d = 6.0 adc) g fs 7.0 mhos dynamic characteristics input capacitance (v 25 vd v 0vd c iss 390 550 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss 115 160 reverse transfer capacitance f = 1 . 0 mhz) c rss 35 70 switching characteristics (notes 4 & 5) turnon delay time t d(on) 11 20 ns rise time (v dd = 80 vdc, i d = 12 adc, t r 30 60 turnoff delay time (v dd 80 vdc , i d 12 adc , v gs = 10 vdc, r g = 9.1 w ) t d(off) 22 40 fall time t f 32 60 total gate charge (v 80 vd i 12 ad q tot 14 20 nc gatetosource charge (v ds = 80 vdc, i d = 12 adc, v gs = 10 vdc ) q gs 3.0 gatetodrain charge v gs = 10 vdc) q gd 7.0 bodydrain diode ratings (note 4) diode forward onvoltage (i s = 12 adc, v gs = 0 vdc) (i s = 12 adc, v gs = 0 vdc, t j = 125 c) v sd 0.95 0.80 1.0 vdc reverse recovery time (i 12 ad v 0vd t rr 85 ns (i s = 12 adc, v gs = 0 vdc, di s /dt = 100 a/ m s ) t a 60 di s /dt = 100 a/ m s) t b 28 reverse recovery stored charge q rr 0.3 m c 4. indicates pulse test: p.w. = 300 m s max, duty cycle = 2%. 5. switching characteristics are independent of operating junction temperature.
ntd12n10 http://onsemi.com 3 typical electrical characteristics 24 12 8 4 10 7 6 5 4 3 2 1 0 0 89 16 20 i d , drain current (amps) 0 figure 1. onregion characteristics v ds , draintosource voltage (volts) 24 12 8 4 10 7 6 5 4 3 2 1 0 figure 2. transfer characteristics v gs , gatetosource voltage (volts) 0 figure 3. onresistance versus drain current and temperature i d , drain current (amps) 0.5 0.4 0.3 0.1 8 4 0 figure 4. onresistance versus drain current and gate voltage i d , drain current (amps) 8 4 0 0.175 0.15 0.125 0.1 0 0.2 figure 5. onresistance variation with temperature t j , junction temperature ( c) 3 1.5 1 0.5 175 125 100 75 50 25 0 25 50 v ds , draintosource voltage (volts) 30 20 1000 100 10 0 10000 figure 6. draintosource leakage current versus voltage i d , drain current (amps) r ds(on) , draintosource resistance ( ) 24 12 0.2 r ds(on) , draintosource resistance ( ) 24 r ds(on), draintosource resistance (normalized) i dss , leakage (na) 40 100 89 20 60 50 70 80 90 v gs = 10 v 4.5 v 5 v 5.5 v 7 v 6 v 9 v t j = 25 c 7.5 v t j = 25 c t j = 55 c t j = 100 c t j = 25 c t j = 55 c t j = 100 c v gs = 10 v t j = 25 c v gs = 10 v i d = 6 a v gs = 10 v t j = 150 c v gs = 0 v t j = 100 c 16 20 6.5 v 8 v 16 20 v gs = 15 v 12 16 v ds 10 v 2 2.5 150
ntd12n10 http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. 25 20 15 10 5 0 5 10 gatetosource or draintosource voltage (volts) figure 7. capacitance variation 1000 600 200 0 v gs v ds 800 400 v gs = 0 v v ds = 0 v t j = 25 c c rss c iss c oss c rss c iss c, capacitance (pf)
ntd12n10 http://onsemi.com 5 i s , source current (amps) t, time (ns) v ds , draintosource voltage (volts) v gs , gatetosource voltage (volts) 12 0 1 0.4 draintosource diode characteristics v sd , sourcetodrain voltage (volts) figure 8. gatetosource and draintosource voltage versus total charge figure 9. resistive switching time variation versus gate resistance r g , gate resistance ( w ) 1 10 100 1000 1 v dd = 80 v i d = 12 a v gs = 10 v v gs = 0 v t j = 25 c figure 10. diode forward voltage versus current 100 20 0 18 0 q g , total gate charge (nc) 20 414 8 0 100 210 612 i d = 12 a t j = 25 c v gs q 2 q 1 q t v ds t r t d(off) t d(on) t f 16 12 14 10 8 6 2 4 90 10 80 70 60 50 40 30 10 2 4 6 8 10 0.5 0.6 0.7 0.8 0.9 safe operating area the forward biased safe operating area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistancegeneral data and its use.o switching between the offstate and the onstate may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. although many efets can withstand the stress of draintosource avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated.
ntd12n10 http://onsemi.com 6 safe operating area r(t), effective transient thermal resistance (normalized) e as , single pulse draintosource avalanche energy (mj) i d , drain current (amps) t j , starting junction temperature ( c) 0.1 1 v ds , draintosource voltage (volts) 1 100 r ds(on) limit thermal limit package limit 0.1 0 25 50 75 100 125 4 0 i d = 12 a 10 10 175 20 6 0 80 100 v gs = 20 v single pulse t c = 25 c 1 ms 100 m s 10 ms dc 10 m s t, time (s) 0.1 1.0 0.01 0.1 0.2 0.02 d = 0.5 0.05 0.01 single pulse r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 110 0.1 0.01 0.001 0.0001 0.00001 figure 11. maximum rated forward biased safe operating area figure 12. maximum avalanche energy versus starting junction temperature figure 13. thermal response di/dt t rr t a t p i s 0.25 i s time i s t b figure 14. diode reverse recovery waveform 150
ntd12n10 http://onsemi.com 7 information for using the dpak surface mount package recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.190 4.826 mm inches 0.100 2.54 0.063 1.6 0.165 4.191 0.118 3.0 0.243 6.172 power dissipation for a surface mount device the power dissipation for a surface mount device is a function of the drain pad size. these can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . using the values provided on the data sheet, p d can be calculated as follows: p d = t j(max) t a r q ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device. for a dpak device, p d is calculated as follows. p d = 150 c 25 c 71.4 c/w = 1.75 watts the 71.4 c/w for the dpak package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 watts. there are other alternatives to achieving higher power dissipation from the surface mount packages. one is to increase the area of the drain pad. by increasing the area of the drain pad, the power dissipation can be increased. although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. for example, a graph of r q ja versus drain pad area is shown in figure 15. figure 15. thermal resistance versus drain pad area for the dpak package (typical) a, area (square inches) r , thermal resistance, junction to ambient (c/w) q ja 80 100 60 40 20 10 8 6 4 2 0 3.0 watts 5.0 watts t a = 25 c 1.75 watts board material = 0.0625 g-10/fr-4, 2 oz copper
ntd12n10 http://onsemi.com 8 another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad . using a board material such as thermal clad, an aluminum core board, the power dissipation can be doubled using the same footprint. solder stencil guidelines prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. solder stencils are used to screen the optimum amount. these stencils are typically 0.008 inches thick and may be made of brass or stainless steel. for packages such as the sc59, sc70/sot323, sod123, sot23, sot143, sot223, so8, so14, so16, and smb/smc diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. this is not the case with the dpak and d 2 pak packages. if one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or atombstoningo may occur due to an excess of solder. for these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. the opening for the leads is still a 1:1 registration. figure 16 shows a typical stencil for the dpak and d 2 pak packages. the pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. ?? ?? ?? ?? ??? ??? ??? ??? ??? ??? ??? ??? ?? ?? figure 16. typical stencil for dpak and d 2 pak packages solder paste openings stencil soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * due to shadowing and the inability to set the wave height to incorporate other surface mount components, the d 2 pak is not recommended for wave soldering.
ntd12n10 http://onsemi.com 9 typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones, and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 5 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 17. typical solder heating profile
ntd12n10 http://onsemi.com 10 package dimensions style 2: pin 1. gate 2. drain 3. source 4. drain d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h t seating plane z dim min max min max millimeters inches a 0.235 0.250 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.033 0.040 0.84 1.01 f 0.037 0.047 0.94 1.19 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.175 0.215 4.45 5.46 s 0.020 0.050 0.51 1.27 u 0.020 --- 0.51 --- v 0.030 0.050 0.77 1.27 z 0.138 --- 3.51 --- notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 123 4 dpak case 369a13 issue ab
ntd12n10 http://onsemi.com 11 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. style 2: pin 1. gate 2. drain 3. source 4. drain 123 4 v s a k t seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.250 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.033 0.040 0.84 1.01 f 0.037 0.047 0.94 1.19 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.175 0.215 4.45 5.46 s 0.050 0.090 1.27 2.28 v 0.030 0.050 0.77 1.27 dpak case 36907 issue m
ntd12n10 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ntd12n10/d thermal clad is a registered trademark of the bergquist company. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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